A common requirement in integrated circuit fabrication is plasma etching of openings such as contacts, vias and trenches in dielectric materials. The dielectric materials include doped silicon oxide such as fluorinated silicon oxide, undoped silicon oxide, silicate glasses such as boron phosphate silicate glass (BPSG) and phosphate silicate glass (PSG), doped or undoped thermally grown silicon oxide, doped or undoped TEOS deposited silicon oxide, organic and inorganic low-k materials, etc. The dielectric dopants include boron, phosphorus and/or arsenic.
The dielectric can overlie a semiconductive or conductive layer such as polycrystalline silicon; metals such as aluminum, copper, titanium, tungsten, molybdenum or alloys thereof; nitrides such as titanium nitride; metal silicides such as titanium silicide, cobalt silicide, tungsten silicide, molybdenum silicide, etc.
Using conventional photolithography a layer of photoresist and/or a hard mask can be used to pattern the dielectric. Optionally, an anti-reflective coating (ARC) deposited beneath the photoresist layer may be used in order to minimize reflection during resist exposure and improve the fidelity of the resist pattern.
Vacuum processing chambers are generally used for etching of materials on substrates by supplying process gas to the vacuum chamber and application of an RF field to the gas. Plasma etching can be carried out, for example, in medium density reactors such as the parallel plate plasma reactor chambers described in U.S. Pat. Nos. 4,340,462 and 5,013,398 or the triode-type reactors described in U.S. Pat. No. 5,013,400.
Techniques to achieve profile control of deep openings having high aspect ratios of at least 5:1 are disclosed in commonly owned U.S. Pat. Nos. 6,117,786 and 6,191,043. Of these, the '786 patent discloses etching of openings in silicon oxide layers using a gas mixture containing fluorocarbon, oxygen and nitrogen reactants wherein the oxygen and nitrogen are added in amounts effective to control the profile of the etched opening. The '043 patent discloses etching of deep openings 10 to 15 μm deep in a silicon layer by using a chlorine-containing etch gas chemistry to etch through a native oxide layer over the silicon layer and using a gas mixture containing an oxygen reactant gas, helium, an inert bombardment-enhancing gas and a fluorine-containing gas such as SF6, C4F8, CF4, NF3 and CHF3 to etch the silicon layer.
Conventionally, fluorocarbon, hydrofluorocarbon, and/or chlorofluorocarbon-based etch gases have been widely used to etch dielectric layers because the F and Cl constituents facilitate etching both via a radical reaction and an ion-assisted reaction while sidewall protection is afforded using carbonaceous polymers formed on the surface of the substrate.
Selectivity is desirable with respect to overlying photoresist, hardmask, and ARC layers as well as the bottom etch stop layer. Selectivity is especially desirable at the corners of a patterned photoresist or hardmask layer because the corners have a geometry favorable to fast etching that tends to create facets which undesirably impact the critical dimensions of the feature. Photoresist/hardmask faceting can lead to via/trench “blowout” of device critical dimensions, while low selectivity to etch stop layers may lead to significant sputtering onto the via sidewall. Accordingly, there is a need in the art for a plasma etching technique which achieves high photoresist or hardmask etch selectivity, high dielectric etch rate, low pollution and low damage. More particularly, there is a need for a plasma process which enhances photoresist to oxide etch selectivity in order to achieve a highly anisotropic dielectric etch with minimal damage or distortion of the original photoresist pattern.